1. Field of the Invention
The present invention relates to a buffer circuit which transfers data held in a first latch circuit to a second latch circuit.
2. Description of Related Art
FIG. 14 is a circuit diagram showing a conventional buffer circuit. In this figure, the reference numerals 1 and 2 each designate a signal line; 3 and 4 each designate a control signal line; 5 designates a bistable latch circuit; 6 designates an inverter for inverting the output of an inverter 7 which in turn inverts the output of the inverter 6; and 8 and 9 each designate an NMOS transistor which has its gate electrode connected to the control signal line 3, and which transfers to a nonconducting state when the signal level of the control signal line 3 falls to L level (the ground level), and to a conducting state when the signal level rises to H level (a supply voltage level).
The reference numerals 10-13 each designate a power supply; 14 and 15 each designate a PMOS transistor which has its gate electrode connected to the control signal line 4, and which changes into conducting state when the signal level of the control signal line 4 is placed at L level, and into nonconducting state when the signal level of the control signal line 4 is placed at H level; 16 designates a PMOS transistor which has its gate electrode connected to the signal line 2, and which changes into the conducting state when the signal level of the signal line 2 is placed at L level, and changes into the nonconducting state when the signal level of the signal line 2 is placed at H level; and 17 designates a PMOS transistor which has its gate electrode connected to the signal line 1, and which changes into the conducting state when the signal level of the signal line 1 is placed at L level, and changes into the nonconducting state when the signal level of the signal line 1 is placed at H level.
The reference numeral 18 designates a latch circuit for holding data transferred from the latch circuit 5, 19 designates an NAND gate having a first input terminal connected to the signal line 1 and a second input terminal connected to the output terminal of an NAND gate 20 which in turn has its first input terminal connected to the signal line 2 and its second input terminal connected to the output terminal of the NAND gate 19.
Next, the operation will be described separately for the two cases: A first term (non-transfer mode) during which the signal levels of the control signal lines 3 and 4 are both L level; and a second term (transfer mode) during which they are both H level.
First, the operation in the first term will be described with reference to FIG. 15 which shows signal levels of various portions and the state of the transistors. Here, it is assumed for convenience' sake that the output of the inverter 6 is L level and the output of the inverter 7 is H level.
First, since the signal level of the control signal line 3 is L level during the first term, the signal levels of the gate electrodes of the NMOS transistors 8 and 9 are L level, and hence the NMOS transistors 8 and 9 are placed at the nonconducting state.
Accordingly, the latch circuit 5 is isolated from the signal lines 1 and 2, and the data of the latch circuit 5 cannot be transferred to the latch circuit 18 in the first term.
In addition, since the signal level of the control signal line 4 is L level, the signal levels of the gate electrodes of the PMOS transistors 14 and 15 are L level, and hence the PMOS transistors 14 and 15 are placed at the conducting state.
Accordingly, the power supply 10 is connected to the signal line 1 through the PMOS transistor 14, and the power supply 11 is connected to the signal line 2 through the PMOS transistor 15, thereby raising the signal levels of the signal lines 1 and 2 to H level.
Therefore, the H level signals are input to the first input terminals of the NAND gates 19 and 20 (the input terminals connected to the signal lines 1 and 2) which constitute the latch circuit 18. Accordingly as shown in FIG. 15, if the NAND gate 19 outputs an L level signal, the NAND gate 20 outputs an H level signal. Reversely, if the NAND gate 19 outputs an H level signal, the NAND gate 20 outputs an L level signal.
This means that the latch circuit 18 maintains holding the prestored data independently of the data held by the latch circuit 5 in the first term.
Second, the operation in the second term will be described with reference to FIG. 16 which shows signal levels of various portions and the state of the transistors. Here, it is assumed for convenience' sake that the output of the inverter 6 is L level and the output of the inverter 7 is H level.
First, since the signal level of the control signal line 3 is H level during the second term, the signal levels of the gate electrodes of the NMOS transistors 8 and 9 are H level, and hence the NMOS transistors 8 and 9 are placed at the conducting state.
Accordingly, the latch circuit 5 is connected to the signal lines 1 and 2, so that the data of the latch circuit 5 can be transferred to the latch circuit 18 in the second term.
In addition, since the signal level of the control signal line 4 is also H level, the signal levels of the gate electrodes of the PMOS transistors 14 and 15 are H level, and hence the PMOS transistors 14 and 15 are placed at the nonconducting state.
Accordingly, the signal line 1 is isolated from the power supply 10, and the signal level of the signal line 1, affected by the signal level of the output of the inverter 7, is placed at H level.
Likewise, the signal line 2 is isolated from the power supply 11, and the signal level of the signal line 2, affected by the signal level of the output of the inverter 7, is placed at L level.
In this case, since the signal level of the signal line 2 in the first term has been placed at H level, it must be changed to L level by discharging the voltage applied to the signal line 2 through the inverters 6 and 7.
Thus, the H level signal is input to the first input terminal of the NAND gate 19 (the input terminal connected to the signal line 1), and the L level signal is input to the first input terminal of the NAND gate 20 (the input terminal connected to the signal line 2). Accordingly, the NAND gate 20 outputs an H level signal, and the NAND gate 19 outputs an L level signal.
This means that the NAND gate 19 of the latch circuit 18 holds the same data as that held in the inverter 6 of the latch circuit 5, and the NAND gate 20 of the latch circuit 18 holds the same data as that held in the inverter 7 of the latch circuit 5.
The conventional latch circuit thus arranged can transfer the data held by the inverters 6 and 7 constituting the latch circuit 5 to the latch circuit 18. This, however, presents a problem in that high speed data transfer can be hindered during the transition from the first term to the second term because the time taken by the discharge through the inverters 6 and 7 cannot be ignored when the parasitic capacitance of the signal lines 1 and 2 is not negligible.